The present invention relates generally to the field of electrical buses. More particularly, the present invention relates to a current driver for a high speed bus.
Computer systems and other electronic systems typically use buses for interconnecting integrated circuit components so that the components may communicate with one another. The buses frequently connect a master, such as a microprocessor or controller, to slaves, such as memories and bus transceivers. Generally, a master may send data to and receive data from one or more slaves. A slave may send data to and receive data from a master, but not another slave.
Each master and slave coupled to a prior bus typically includes output driver circuitry for driving signals onto the bus. Some prior bus systems have output drivers that use transistor-transistor logic (xe2x80x9cTTLxe2x80x9d) circuitry. Other prior bus systems have output drivers that include emitter-coupled logic (xe2x80x9cECLxe2x80x9d) circuitry. Other output drivers use complementary metal-oxide-semiconductor (xe2x80x9cCMOSxe2x80x9d) circuitry or N-channel metal-oxide-semiconductor (xe2x80x9cNMOSxe2x80x9d) circuitry.
While many prior buses were driven by voltage level signals, it has become advantageous to provide buses that are driven by a current mode output driver. A benefit associated with a current mode driver is a reduction of peak switching current. In particular, the current mode driver draws a known current regardless of load and operating conditions. A further benefit is that the current mode driver typically supresses noise coupled form power and ground supplies.
A known current mode driver is shown in U.S. Pat. No. 5,254,883 (the xe2x80x9c""883 patentxe2x80x9d), which is assigned to the assignee of the present invention and incorporated herein by reference. The ""883 patent discusses an apparatus and method for setting and maintaining the operating current of a current mode driver. The driver in the ""883 patent includes an output transistor array, output logic circuitry coupled to the transistor array and a current controller coupled to the output logic circuitry.
For one embodiment, the current controller in the ""883 patent is a resistor reference current controller. The current controller receives two input voltages, VTERM and VREF, the latter of which is applied to an input of a comparator. VTERM is coupled by a resistor to a node, which is in turn coupled to a second input of the comparator. The voltage at the node is controlled by a transistor array, which is in turn controlled in accordance with an output of the comparator.
When the transistor array is placed in the xe2x80x9coffxe2x80x9d state, i.e. there is no current flowing through the transistors of the array to ground, the voltage at the node is equal to VTERM. In addition, by using the output of the comparator to adjustably activate the transistor array, the ""883 patent shows that the voltage at the node may be driven to be approximately equal to the reference voltage, VREF.
Knowing the value of VREF and VTERM, the current mode driver of the ""883 patent therefore provides a binary signaling scheme utilizing a symmetrical voltage swing about VREF. Specifically, in a first current state (the xe2x80x9coffxe2x80x9d state), the current mode driver is not sinking current and the signal line (or bus line) is at a voltage, Vo=VTERM, representing a logical xe2x80x9c0.xe2x80x9d In a second current state (the xe2x80x9conxe2x80x9d state), the current mode driver is sinking current to drive the voltage on the signal line (or bus line) to be:
Vo=VTERMxe2x88x922(VTERMxe2x88x92VREF).
The second state therefore representing a logical xe2x80x9c1.xe2x80x9d
While the above techniques have met with substantial success, end users of data processing systems, such as computers, continue to demand increased throughput. Whether throughput is expressed in terms of bandwidth, processing speed or any other measure, the bottom line is the desire to get a block of data from point A to point B faster. At the same time, however, it is desirable to achieve such increases without requiring deviation from known semiconductor fabrication techniques.
A multi-level driver uses multiple pulse amplitude modulation (multi-PAM) output drivers send multi-PAM signals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a xe2x80x9csymbolxe2x80x9d at one of the valid voltage levels. In one embodiment, a symbol represents two or more bits. The multi-PAM output driver drives an output symbol into a signal line. The output symbol represents at least two bits that include a most significant bit (MSB) and a least significant bit (LSB). A multi-PAM receiver receives the output symbol from the signal line and determines the MSB and the LSB.
In accordance with a first aspect of the invention, a current controller for a multi-level current mode driver is provided. The current controller includes a multi-level voltage reference and at least one source calibration signal. A comparator is coupled by a coupling network to the multi-level voltage reference and the at least one source calibration signal. The current controller further includes a circuit for applying a selected voltage from the multi-level voltage reference and a selected source calibration signal from the at least one source calibration signal to the comparator.
In accordance with a second aspect of the invention, a method of calibrating a multi-level current mode driver is provided. The method includes two current sinks, each capable of sinking current from a termination voltage though a resistor. The first current sink drives a known amount of current through a resistor producing a first input signal. The second current sink is turned on to produce a second input signal. An average value of the first input signal and the second input signal is calculated. The average value of the first input signal and the second input signal is compared to a first known reference voltage. And, the second current sink, and thereby the second input signal, is adjusted until the average value equals the known reference voltage.